The manufacture of integrated circuit devices involves the formation of wells and other regions in a substrate that are doped with various impurities, such as Boron, Arsenic and Phosphorus. These regions form the site where transistor and transistor components will be fabricated. Regions that are doped with n-type impurities, such as Phosphorus or Arsenic, give rise to p-channel transistors, whereas regions lying outside of n-wells (called p-wells) that are doped with p-type impurities, such as Boron, provide a site for fabricating n-channel transistors. Both n-channel and p-channel transistors are required to implement CMOS technology.
Integrated circuit manufacture provides for the formation of active regions that are separated by distances of about 1 .mu.m or greater by field oxide layers having a thickness of about 400-1200 nm. Transistors and other electrical structures are formed in the active regions. The field oxide provides for electrical isolation between separate and distinct electrical device regions on a die.
As the state of the art advances, a greater number of circuit components are to be provided on smaller surface areas of the die. However, as die size and die component separation are reduced, it becomes increasingly difficult to maintain electrical isolation between electronic components formed on the die, due principally to the problem of lateral diffusion when diffusion principally in the vertical direction is desired. Undesired vertical diffusion is also problematic, especially in devices having junctions on the order of 0.1 .mu.m or less. As thermal processing tends to drive junctions deeper into the substrate, device performance can be compromised. This is especially true during high temperature annealing, which is required to activate impurities implanted in the transistor service/drain regions.
It is well known that Boron and Phosphorus diffuse predominantly by interactions with silicon interstitials. In contrast, Arsenic and Antimony are known to diffuse principally through interactions with lattice vacancies. Therefore, the manner in which the dopant diffuses into the semiconductor device affects not only the structure of the adjacent regions into which the dopant diffuses, but also the measures that one can take to minimize the extent of dopant diffusion. For example, measures taken to inhibit Boron or Phosphorus diffusion could not be expected to have the same impact upon diffusion of Arsenic or Antimony. Likewise, measures taken to inhibit Boron or Phosphorus diffusion could not be expected to have the impact upon diffusion of Arsenic or Antimony, as Arsenic and Antimony diffuse by way of a different mechanisms (lattice vacancies) as opposed to Boron and Phosphorus (interstitials). Moreover, Boron (for p+ source/drains) and Phosphorus (for n+ source/drains) are among the fastest diffusing impurities. Accordingly, as Boron and Phosphorus are widely used for fabricating transistor source/drains, it is desirable to minimize the concentration of substrate interstitials during source/drain annealing. In cases where both Arsenic and phosphorus are used in forming N+ source/drain regions, the faster diffusing species is phosphorus. Therefore, measures taken to reduce Boron and phosphorus diffusion are effective in reducing the overall N+ junction depth.
In conventional CMOS manufacture, active regions are formed by a local oxidation process in which a thin layer of SiO.sub.2 is grown in a diffusion furnace and a silicon nitride (Si.sub.3 N.sub.4) layer is deposited by low pressure chemical vapor deposition ("LPCVD") over the SiO.sub.2. The oxide/nitride stack functions as an oxidation blocking layer above what will become the active region of the device. Prior to development of a field oxide outside of the blocking layer, Boron is implanted into areas where the field oxide is to be grown, but not into active regions which are covered by oxide/nitride/photoresist stack. As the Boron is driven into the semiconductor device, the Boron freely diffuses vertically and laterally (by interstitials) into the active region, compromising region integrity for the development of circuit devices.
The problem of dopant diffusion during well drive-in is well documented. Lateral dopant diffusion of approximately 80% well depth is acknowledged in CMOS Well Drive-In in NH.sub.3 for Reduced Lateral Diffusion and Heat Cycle, IEEE Electron Device Letters, v. EDL-6, no. 12, Dec. 1985. The stated consequence of such undesired diffusion is an increase in the spacing requirement between the well and complementary MOSFET's outside of the well. The article reports retardation of lateral diffusion through the use of an ammonia ambient. Well drive-in is performed at 1,125.degree. C. in either an N.sub.2 or an NH.sub.3 ambient. With reference to the ammonia ambient, the authors assert that silicon vacancies are generated at the SiO.sub.2 -substrate interface on the well regions where oxynitridation occurs, thus inhibiting lateral Phosphorus diffusion. Increased silicon vacancy concentration causes a decreased silicon interstitial concentration because the product of Si vacancies times interstitials is equal to an equilibrium constant. The reduced concentration of self-interstitials in the lateral direction is believed to inhibit lateral diffusion of Phosphorus.
More recently, the importance of scaling parasitic dimensions such as isolation regions and well dimensions has been addressed in Reduction of Lateral Phosphorus Diffusion in CMOS n-Wells, IEEE Transactions on Electron Devices, v. 37, no. 3, March 1990. Lateral diffusion of dopants during drive-in is identified as a primary factor that limits packaging density of semiconductor devices. Lateral diffusion of Phosphorus is reduced by creating silicon interstitial undersaturation in the region where the Phosphorus atoms diffuse laterally, as such Phosphorus atoms diffuse predominantly by interaction with self-interstitials. Lateral diffusion of Phosphorus is controlled by creating vacancy supersaturation arising from the decomposition reaction of SiO.sub.2 ultimately to SiO, which results in the consumption of silicon atoms. The known prior art, however, does not address the problem of source/drain drive-in incident to the anneal process for activating implanted dopants and for repairing crystalline lattice damage arising from dopant implantation. This problem becomes particularly acute as industry plans for the development of sub-micron technology.